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INTEGRATED CIRCUITS
DATA SHEET
TDA9874A Digital TV sound demodulator/decoder
Preliminary specification File under Integrated Circuits, IC02 1999 Dec 03
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
CONTENTS 1 2 2.1 3 4 5 6 6.1 6.2 6.3 7 8 9 10 10.1 10.2 10.3 10.4 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 FEATURES GENERAL DESCRIPTION Supported standards ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section Description of the DSP Description of the analog audio section LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS I2C-BUS CONTROL Introduction Power-up state Slave receiver mode Slave transmitter mode I2S-BUS DESCRIPTION EXTERNAL COMPONENTS PACKAGE OUTLINES SOLDERING Introduction Through-hole mount packages Surface mount packages Suitability of IC packages for wave, reflow and dipping soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
TDA9874A
1999 Dec 03
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
1 FEATURES
TDA9874A
* Sound IF (SIF) input switch * SIF AGC with 24 dB control range * Switchable 10 dB SIF input attenuator * SIF 8-bit Analog-to-Digital Converter (ADC) * Easy TV standard programming option * Differential Quadrature Phase Shift Keying (DQPSK) demodulation for different standards, simultaneously with 1-channel FM demodulation * NICAM decoding (B/G, D/K, I and L standard) * 2-carrier multi-standard FM demodulation (B/G, D/K and M standard) * Single carrier high deviation FM mono demodulation mode * Decoding for three analog multi-channel systems (A2) and satellite sound * Adaptive de-emphasis for satellite * Programmable identification (B/G, D/K and M standard) and different identification times * FM pilot carrier presence detector * Optional AM demodulation for system L, simultaneously with NICAM * Monitor selection for FM/AM demodulator outputs and FM and NICAM signals with peak option * Automatic FM dematrixing option * Digital crossbar switch * I2S-bus serial audio output with matrix, level adjustment and mute * Dual audio Digital-to-Analog Converter (DAC) from digital crossbar switch to analog crossbar switch, bandwidth = 15 kHz * Automatic Volume Level (AVL) control * Analog crossbar switch with inputs for mono and stereo * Output selection of mono, stereo, dual, dual A or dual B * Additional mono output with automatic select * 20 kHz bandwidth for analog path * Standby mode * Automatic output selection for TV applications. 2 GENERAL DESCRIPTION
The TDA9874A is a single-chip Digital TV Sound Demodulator/Decoder (DTVSD) for analog and digital multi-channel sound systems in TV/VCR sets and satellite receivers. 2.1 Supported standards
The multi-standard/multi-stereo capability of the TDA9874A is of interest in Europe, Hong Kong/PR China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas subsets of the standard combinations are available or, only single standards are transmitted. All A2 (analog 2-carrier) and NICAM systems are supported. M standard (with mono or BTSC stereo sound) can be received and processed in mono sound mode. The AM sound of L/L' standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9874A. A second possibility is to use the internal AM demodulator stage (with 6.5 MHz intercarrier), which gives limited performance. Korea has a stereo sound system similar to Europe and is supported by the TDA9874A. The differences include deviation, modulation contents and identification. It is based on M standard. For all FM standards a high deviation mode for a single carrier monaural sound demodulation is selectable. An overview of the supported standards and sound systems and their key parameters is given in Tables 1 to 3. The analog multi-channel systems are sometimes also called 2CS (2-carrier systems).
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
2.1.1 Table 1 ANALOG 2-CARRIER SYSTEMS Frequency modulation SOUND SYSTEM mono A2 A2 mono A2 A2 A2 CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.0 6.5/6.742 6.5/6.258 6.5/5.742 FM DEVIATION (kHz) NOM. 15 15 27 27 27 27 27 MAX. 25 25 50 50 50 50 50 OVER. 50 50 80 80 80 80 80
1 1 1 1 1
TDA9874A
MODULATION SC1 mono
2(L + R) 2(L 1
STANDARD M M B/G I D/K (2) D/K (1) D/K (3) Table 2
SC2 -
2(L - R)
BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50 15/50
+ R)
R - R R R
mono
2(L + R) 2(L 2(L
+ R) + R)
Identification for A2 systems PARAMETER A2; A2* 54.6875 kHz = 3.5 x line frequency line frequency 117.5 Hz = -------------------------------------133 line frequency 274.1 Hz = -------------------------------------57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency line frequency 149.9 Hz = -------------------------------------105 line frequency 276.0 Hz = -------------------------------------57 50%
Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth 2.1.2 Table 3
2-CARRIER SYSTEMS WITH NICAM NICAM SC1 MODULATION SC2 DEROLLNICAM (MHz) EMPHASIS OFF (%) CODING NICAM
STANDARD
FREQUENCY TYPE (MHz)
INDEX (%) NOM. MAX. - - - 100
DEVIATION (kHz) NOM. 27 27 27 - MAX. 50 50 50 -
B/G I D/K L Notes
5.5 6.0 6.5 6.5
FM FM FM AM
- - - 54
5.85 6.552 5.85 5.85
J17 J17 J17 J17
40 100 40 40
note 1 note 1 note 2 note 1
1. See "EBU NICAM 728 specification" or equivalent specification. 2. Not yet officially defined.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
2.1.3 SATELLITE SYSTEMS
TDA9874A
An important specification for satellite TV reception is the Astra specification. The TDA9874A is suitable for the reception of Astra and other satellite signals, with sound carrier frequencies from 4 to 9.2 MHz. Table 4 FM satellite sound CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 Notes 1. For other satellite systems, frequencies of e.g. 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 s, or in accordance with J17, is available. 2. Main channels with high deviation can also be handled. 3. m/st/d = mono or stereo or dual language sound. 4. Adaptive de-emphasis is compatible to transmitter specification. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9874APS TDA9874AH SDIP42 QFP44 DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm VERSION SOT270-1 SOT205-1 MODULATION INDEX 0.26 0.15 MAXIMUM FM DEVIATION (kHz) 85(2) 50 MODULATION mono m/st/d(3) BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/50(1) 15/adaptive(4)
CARRIER TYPE Main Sub
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
4 BLOCK DIAGRAM
TDA9874A
handbook, full pagewidth
SIF2 27 (23)
SIF1 29 (25) (21) 25 (20) 24 (28) 32 (27) 31 (24) 28 (18) 22 VDEC VSSA2 VDDA3 VSSA3 Vref1 Iref
P1 P2 ADDR1 ADDR2 SCL SDA
41 (37) 4 (42) 18 (13) 23 (19) 33 (29) 34 (30) I2C-BUS INTERFACE SUPPLY SIF
INPUT SWITCH AGC, ADC
IDENTIFICATION
FM/AM DEMODULATION
(10) 15 NICAM DEMODULATION (12) 17 (8)
NICAM PCLK n.c.
XTALI XTALO SYSCLK
20 (15) 19 (14) 38 (34) CLOCK DEMATRIX NICAM DECODER DIGITAL SUPPLY PEAK DETECTION 2-CHANNEL ANALOG/ SATELLITE DECODER LEVEL ADJUST
(7) 13 (6) 12 (5) 11 (35) 39 (36) 40 (26) 30
VSSD2 VDDD1 VSSD1 VDDD3 VSSD3 CRESET
(3) 9 35 (31) 36 (32) 37 (33) I2S-BUS INTERFACE DIGITAL SELECTOR POST FILTER 3 DACs REFERENCE SUPPLY DACs OPAMPS (4) 10 (44) 6 (41) 3
VDDA1 VSSA1 VSSA4 Vref 2 EXTIR EXTIL MONOIN
SDO WS SCK
TDA9874APS (TDA9874AH)
TEST1 TEST2 TP1 TP2 TP3 26 (22) 21 (17) 16 (11) 14 (9) (16) TEST
(39) 1 ANALOG CROSSBAR SWITCH (40) 2 (38) 42
MONO CHANNEL OUTPUT BUFFERS 5 (43) OUTM
2-CHANNEL OUTPUT BUFFERS 7 (1) OUTL 8 (2)
MHB584
OUTR
The pin numbers given in parenthesis refer to the TDA9874AH.
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
5 PINNING PIN SYMBOL SDIP42 EXTIR EXTIL Vref2 P2 OUTM VSSA4 OUTL OUTR VDDA1 VSSA1 VSSD1 VDDD1 VSSD2 n.c. TP2 NICAM TP1 PCLK ADDR1 XTALO XTALI TP3 TEST2 Iref ADDR2 VSSA2 VDEC TEST1 SIF2 Vref1 SIF1 CRESET VSSA3 VDDA3 SCL SDA SDO WS 1 2 3 4 5 6 7 8 9 10 11 12 13 - 14 15 16 17 18 19 20 - 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 QFP44 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 external audio input right channel external audio input left channel DESCRIPTION
TDA9874A
analog reference voltage for DAC and operational amplifiers second general purpose I/O pin analog output right analog ground supply 4 for analog back-end circuitry analog output left analog output right analog supply voltage 1; back-end circuitry 5 V analog ground supply 1; back-end circuitry digital ground supply 1; core circuitry digital supply voltage 1; core voltage regulator circuitry digital ground supply 2; core circuitry not connected additional test pin 2; connected to VSSD for normal operation serial NICAM data output (at 728 kHz) additional test pin 1; connected to VSSD for normal operation NICAM clock output (at 728 kHz) first I2C-bus slave address modifier input crystal oscillator output crystal oscillator input additional test pin 3; connected to VSSD for normal operation test pin 2; connected to VSSD for normal operation resistor for reference current generation; front-end circuitry second I2C-bus slave address modifier input analog ground supply 2; analog front-end circuitry analog front-end circuitry supply voltage decoupling test pin 1; connected to VSSD for normal operation sound IF input 2 reference voltage; for analog front-end circuitry sound IF input 1 capacitor for Power-on reset digital ground supply 3; front-end circuitry analog front-end circuitry regulator supply voltage 3 (5 V) I2C-bus serial clock input I2C-bus serial data input/output I2S-bus serial data output I2S-bus word select input/output
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
PIN SYMBOL SDIP42 SCK SYSCLK VDDD3 VSSD3 P1 MONOIN 37 38 39 40 41 42 QFP44 33 34 35 36 37 38 I2S-bus clock input/output system clock output digital supply voltage 3; digital I/O pads digital ground supply 3; digital I/O pads first general purpose I/O pin analog mono input DESCRIPTION
handbook, halfpage
EXTIR EXTIL Vref2 P2 OUTM VSSA4 OUTL OUTR VDDA1
1 2 3 4 5 6 7 8 9
42 MONOIN 41 P1 40 VSSD3 39 VDDD3 38 SYSCLK 37 SCK 36 WS 35 SDO 34 SDA 33 SCL
VSSA1 10
VSSD1 11 TDA9874APS 32 VDDA3 VDDD1 12 VSSD2 13 TP2 14 NICAM 15 TP1 16 PCLK 17 ADDR1 18 XTALO 19 XTALI 20 TEST2 21
MHB585
31 VSSA3 30 CRESET 29 SIF1 28 Vref1 27 SIF2 26 TEST1 25 VDEC 24 VSSA2 23 ADDR2 22 Iref
Fig.2 Pin configuration (SDIP42).
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
38 MONOIN
35 VDDD3
36 VSSD3
44 VSSA4
handbook, full pagewidth
34 SYSCLK
39 EXTIR
43 OUTM
40 EXTIL
41 Vref2
42 P2
37 P1
OUTL 1 OUTR 2 VDDA1 3 VSSA1 4 VSSD1 5 VDDD1 6 VSSD2 7 n.c. 8 TP2 9 NICAM 10 TP1 11
33 SCK 32 WS 31 SDO 30 SDA 29 SCL
TDA9874AH
28 VDDA3 27 VSSA3 26 CRESET 25 SIF1 24 Vref1 23 SIF2
VDEC 21
ADDR1 13
XTALO 14
TEST2 17
ADDR2 19
VSSA2 20
TEST1 22
PCLK 12
XTALI 15
TP3 16
Iref 18
MHB586
Fig.3 Pin configuration (QFP44).
6 6.1
FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section SIF INPUT
The AGC can be controlled via the I2C-bus; details are given in Sections 10.3.2, 10.3.3 and 10.4.6. 6.1.3 MIXER
6.1.1
Two input pins are provided, SIF1 and SIF2. For higher SIF signal levels the SIF input can be attenuated with an internal switchable -10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 AGC
The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus (see Sections 10.3.5 and 10.3.6) or via Easy Standard Programming (ESP, see Section 10.3.23). When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. 6.1.4 FM AND AM DEMODULATION
The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads, and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen; see Table 16. 1999 Dec 03 9
An FM or AM input signal is fed through a switchable band-limiting filter into a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for Wegener-Panda 1 encoded satellite programs.
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
6.1.5 FM DECODING
TDA9874A
The status of the NICAM decoder can be read out from the NICAM status register by the user (see Section 10.4.2). The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to the sound conveyed by the NICAM channel. The error byte contains the number of sound sample errors (resulting from parity checking) that occurred in the past 128 ms period. The Bit Error Rate (BER) is approximately 0.0000174 times the contents of the error byte: bit errors -5 BER = ---------------------- error byte x 1.74 x 10 total bits 6.1.9 NICAM AUTO-MUTE
A 2-carrier stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. Automatic FM dematrixing is also supported, which means that the FM sound mode identification (mono, stereo or dual) switches the FM dematrix directly. No loop via the microcontroller is needed. For highly overmodulated signals, a high deviation mode for monaural audio sound single carrier demodulation can be selected. NICAM decoding is still possible in high deviation mode. 6.1.6 FM IDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standards, and for three different time constants that represent different trade-offs between speed and reliability of identification. A pilot detector allows the control software to identify an analog 2-carrier (A2) transmission within approximately 0.1 s. Automatic FM dematrixing, depending on the identification, is possible. 6.1.7 NICAM DEMODULATION
This function is enabled by setting bit AMUTE LOW (see Section 10.3.12). Upper and lower error limits may be defined by writing appropriate values to two registers in the I2C-bus section (see Sections 10.3.14 and 10.3.15). When the number of errors in a 128 ms period exceeds the upper error limit, the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM) or to the analog mono input. When the error count is smaller than the lower error limit, the NICAM sound is restored. The auto-mute function can be disabled by setting bit AMUTE HIGH. In this case clicks become audible when the error count increases. The user will hear a signal of degrading quality. If no NICAM sound is received, the outputs are switched from the NICAM channel to the 1st sound carrier. A decision to enable or disable the auto-mute is taken by the microprocessor based on an interpretation of the application control bits C1, C2, C3 and C4, and possibly any additional strategy implemented by the user in the microcontroller software. When the AM sound in NICAM L systems is demodulated in the 1st sound IF and the audio signal connected to the mono input of the TDA9874A, the controlling microprocessor has to ensure switching from NICAM reception to mono input, if auto-muting is desired. This can be achieved by setting the AMSEL bit HIGH and the AMUTE bit LOW (see Section 10.3.12).
The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbits/s. The NICAM demodulator performs DQPSK demodulation and passes the resulting bitstream and clock signal to the NICAM decoder and, for evaluation purposes, to various pins. A timing loop controls the frequency of the crystal oscillator to lock the sampling instants to the symbol timing of the NICAM data. 6.1.8 NICAM DECODING
The device performs all decoding functions in accordance with the "EBU NICAM 728 specification". After locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence. The device then synchronizes to the periodic frame flag bit C0.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
6.1.10 CRYSTAL OSCILLATOR
TDA9874A
It should be noted that the internal ESD protection diode does not help here as it only conducts at higher voltages. Under difficult power supply conditions (e.g. very slow or non-monotonic ramp-up), it is recommended to drive the reset line from a microcontroller port or the like.
The digital controlled crystal oscillator (DCXO) is fully integrated. Only an external 24.576 MHz crystal is required. 6.1.11 TEST PINS
All test pins are active HIGH. In normal operation of the device they can be left open-circuit, as they have internal pull-down resistors. Test functions are for manufacturing tests only and are not available to customers. 6.1.12 POWER FAIL DETECTOR
V handbook, halfpage 5
MHB587
VDDD > 4.5 V
The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the power failure register bit PFR in subaddress 0 (see Section 10.4.1), will be set to HIGH. The CLRPFR bit, slave register subaddress 1 (see Section 10.3.3), resets the Power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9874A has to be performed to ensure reliable operation. 6.1.13 POWER-ON RESET 6.2 6.2.1
1.5
VCRESET < 0.3VDDD reset active guaranteed t
Fig.4 Reset at power-on.
Description of the DSP LEVEL SCALING
The reset is active LOW. In order to perform a reset at power-up, a simple RC circuit may be used which consists of an integrated passive pull-up resistor and an external capacitor connected to ground. The pull-up resistor has a nominal value of 50 k, which can easily be measured between pins CRESET and VDDD3. Before the supply voltage has reached a certain minimum level, the state of the circuit is completely undefined and remains in this undefined state until a reset is applied. The reset is guaranteed to be active when: * The power supply is within the specified limits (4.5 to 5.5 V) * The crystal oscillator (DCXO) is functioning * The voltage at pin CRESET is below 0.3VDDD (1.5 V if VDDD = 5.0 V, typically below 1.8 V). The required capacitor value depends on the gradient of the rising power supply voltage. The time constant of the RC circuit should be clearly larger than the rise time of the power supply [to make sure that the reset condition is always satisfied (see Fig.4)], even when considering tolerance spreading. To avoid problems with a too slow discharging of the capacitor at power-down, it may be helpful to add a diode from the CRESET pin to VDDD.
All input channels to the digital crossbar switch are equipped with a level adjustment facility to change the signal level in a range of 15 dB. Adjusting the signal level is intended to compensate for the different modulation parameters of the various TV standards. Under nominal conditions it is recommended to scale all input channels to be 15 dB below full-scale [-15 dB (FS)]. This will create sufficient headroom to cope with overmodulation and avoids changes of the volume impression when switching from FM to NICAM or vice versa. 6.2.2 NICAM PATH
The NICAM path has a switchable J17 de-emphasis. 6.2.3 NICAM AUTO-MUTE
If NICAM is received, the auto-mute is enabled and the signal quality becomes poor. The digital crossbar switches automatically to FM, channel 1 or the analog mono input, as selected by bit AMSEL. This automatic switching depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
6.2.4 FM (AM) PATH 6.2.7 DIGITAL AUDIO OUTPUT
TDA9874A
A high-pass filter suppresses DC offsets from the FM demodulator that may occur due to carrier frequency offsets, and supplies the FM monitor function with DC values, e.g. for the purpose of microprocessor controlled carrier search or fine tuning functions. An adaptive de-emphasis is available for Wegener-Panda 1 encoded satellite programs. The de-emphasis stage offers a choice of settings for the supported TV standards. The 2-channel decoder performs the dematrixing of 1 (L + R), R to L and R signals of 1 (L + R) and 1 (L - R) 2 2 2 to L and R signals or of channel 1 and channel 2 to L and R signals, as demanded by the different TV standards or user preferences. Automatic FM dematrixing is also supported. Using the high deviation mode, only channel 1 (mono) can be demodulated. The scaling is -6 dB compared to 2-channel decoding. 6.2.5 MONITOR
The digital audio output interface comprises an I2S-bus output port and a system clock output. The I2S-bus port is equipped with a level adjustment facility that can change the signal level in a 15 dB range in 1 dB steps. Muting is possible, too, and outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the functions for forced mono, stereo, channel swap, channel 1 or channel 2. Automatic selection for TV applications is possible. In this case the microcontroller program only has to provide a user controlled sound A or sound B selection. 6.2.8 STEREO CHANNEL TO THE ANALOG CROSSBAR PATH
A level adjustment function is provided with control positions of 0, 3, 6 and 9 dB in combination with the audio DACs. The Automatic Volume Level (AVL) function provides a constant output level of -20 dB (FS) for input levels between 0 and -26 dB (FS). There are some fixed decay time constants to choose from, i.e. 2, 4 or 8 s. Automatic selection for TV applications is possible. In this case the microcontroller program only has to provide a user controlled sound A or sound B selection. 6.2.9 GENERAL
This function provides data words from the FM demodulator outputs and FM and NICAM signals for external use, such as carrier search or fine tuning. The peak level of these signals can also be observed. Source selection and data read-out are performed via the I2C-bus. 6.2.6 DIGITAL CROSSBAR SWITCH
The input channels are derived from the FM and NICAM paths, while the output channels comprise I2S-bus and the audio DACs to the analog crossbar switch. It should be noted that there is no connection from the external analog audio inputs to the digital crossbar switch.
The level adjustment functions can provide signal gain at multiple locations. Great care has to be taken when using gain with large input signals, e.g., due to overmodulation, in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full-scale, i.e., -15 dB (FS).
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1999 Dec 03
NICAM FIXED DE-EMPHASIS
Philips Semiconductors
Digital TV sound demodulator/decoder
LEVEL ADJUST
LEVEL ADJUST stereo DACs
LEVEL ADJUST DIGITAL CROSSBAR SELECT LEVEL ADJUST LEVEL ADJUST MATRIX I2S-bus mono DAC
13
FM
DC FILTER
ADAPTIVE DE-EMPHASIS
FIXED DE-EMPHASIS
2-CHANNEL DECODER
MONITOR
I2C-bus
MHB588
Preliminary specification
TDA9874A
Fig.5 DSP data flow diagram.
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
6.3 6.3.1 Description of the analog audio section ANALOG CROSSBAR SWITCH AND ANALOG MATRIX 6.3.2 EXTERNAL AND MONO INPUTS
TDA9874A
The TDA9874A has one external analog stereo input, one mono input, one 2-channel and one single-channel output port. Analog source selector switches are employed to provide the desired analog signal routing capability, which is done by the analog crossbar switch section. The basic signal routing philosophy of the TDA9874A is that each switch handles two signal channels at the same time (e.g. left and right, language A and B) directly at the source. For an overview of the signal flow see Fig.7. Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels. The analog matrix provides the functions given in Table 5. Automatic matrixing for TV applications is also supported. All switches and matrices are controlled via the I2C-bus. Table 5 Analog matrix functions MATRIX OUTPUT MODE L OUTPUT 1 2 3 4 L input R input L input R input R OUTPUT R input L input L input R input
The external and mono inputs accept signal levels of up to 1.4 V (RMS). By adding external series resistors to provide suitable attenuation, the external input could be used as a SCART input. Whenever the external or mono input is selected, the output of the DAC is muted to improve the crosstalk performance. 6.3.3 AUDIO DACS
The TDA9874A comprises a 2-channel audio DAC and an additional single-channel audio DAC for feeding signals from the DSP section to the analog crossbar switch. These DACs have a resolution of 15 bits and employ four-times oversampling and noise shaping. 6.3.4 AUDIO OUTPUT BUFFERS
The output buffers provide a gain of 0 dB and offer a muting possibility. The post filter capacitors of the audio DACs are connected to the buffer outputs. 6.3.5 STANDBY MODE
The standby mode (see Section 10.3.3) disables most functions and reduces power dissipation of the TDA9874A. It provides no other function. Internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a Power-on reset.
handbook, full pagewidth
source select mono (AM) EXTIL EXTIR
matrix
OUTL
DACL DACR
OUTR
OUTM DACM
MHB589
Fig.6 Switch diagram for the analog audio section.
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mono external ANALOG CROSSBAR SWITCH NICAM DEMODULATOR NICAM DECODER DE-EMPHASIS LEVEL ADJUST DIGITAL CROSSBAR SELECT FM/AM FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS 2-CHANNEL DECODER LEVEL ADJUST LEVEL ADJUST AVL DACs MATRIX BUFFER STEREO OUTPUT NICAM
Philips Semiconductors
handbook, full pagewidth
Digital TV sound demodulator/decoder
MATRIX
BUFFER
MONO OUTPUT
15
MATRIX
LEVEL ADJUST
I2S-bus
MHB590
Preliminary specification
TDA9874A
Fig.7 Audio signal flow.
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDx VDDx IIK IOK IO PARAMETER DC supply voltage voltage differences between two VDDx pins DC input clamp diode current DC output clamp diode current output type 4 mA DC output source or sink current output type 4 mA DC VDDA or VSSA current per analog supply pin latch-up protection current power dissipation per output total power dissipation storage temperature ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 8 THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITIONS in free air Vo < -0.5 V or Vo > VDD + 0.5 V -0.5 V < VO < VDDx + 0.5 V CONDITIONS
TDA9874A
MIN. -0.5 -
MAX. +6.5 550 10 20 20 96 50 - 100 0.75 +125 +70 - -
UNIT V mV mA mA mA mA mA mA mW W C C V V
Vi < -0.5 V or Vi > VDD + 0.5 V - - - - - 100 - - -55 -20 2000 200
IDDD, ISSD DC VDDD or VSSD current per digital supply pin IDDA, ISSA Ilu(prot) P/out Ptot Tstg Tamb Ves
SYMBOL Rth(j-a)
VALUE 70
UNIT K/W
1999 Dec 03
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
9 CHARACTERISTICS VDD = 5 V; Tamb = 25 C; settings in accordance with B/G standard; FM deviation 50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with "EBU NICAM 728 specification"; 1 k measurement source resistance for AF inputs; VSIF = 300 mV (p-p); AGCOFF = 0; AGCSLOW = 1; level and gain settings according to note 1 with external components of Fig.9; unless otherwise specified. SYMBOL Digital supplies VDDD1 VSSD1 IDDD1 VSSD2 VDDD3 VSSD3 IDDD3 digital supply voltage 1 digital ground supply 1 digital supply current 1 digital ground supply 2 digital supply voltage 3 digital ground supply 3 digital supply current 3 VDDD3 = 5.5 V; SYSCLK off VDDD3 = 5.0 V; SYSCLK off Power failure register Vpfr VDDA3 VSSA3 IDDA3 VDEC1 VSSA2 Vref1 Iref1(sink) VDDA1 VSSA1 IDDA1 VSSA4 Vref2 power failure response voltage - 4.5 - VDDA3 = 5.5 V VDDA3 = 5.0 V 24 24 - - - - 4.5 - VDDA1 = 5.5 V VDDA1 = 5.0 V 3 3 - - - 17 4.0 - 5.5 - 40 40 - - - - 5.5 - 10 10 - - - V VDDD1 = 5.5 V VDDD1 = 5.0 V 4.5 - 40 42 - 4.5 - 9 8 5.0 0.0 59 59 0.0 5.0 0.0 17 16 5.5 - 74 75 - 5.5 - 21 20 V V mA mA V V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Demodulator supplies and references analog supply voltage 3, demodulator part analog ground supply 3, demodulator part analog supply current 3, demodulator part analog supply decoupling voltage for front-end analog ground supply 2 analog reference voltage, demodulator part Vref1 sink current analog supply voltage 1, operational amplifiers analog ground supply 1, operational amplifiers analog supply current 1, operational amplifiers analog ground supply 4, audio DAC part reference voltage 2, audio DACs referenced to VDDA1 and and operational amplifiers VSSA1 5.0 0.0 32 32 3.3 0.0 2 200 V V mA mA V V V A V V mA mA V % k
Audio supplies and references 5.0 0.0 6 5 0.0 50 20
Z(Vref2-VDDA3) impedance Vref2 to VDDA3 1999 Dec 03
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
SYMBOL
PARAMETER
CONDITIONS -
MIN.
TYP. 20 -
MAX.
UNIT k
Z(Vref2-VSSA3) impedance Vref2 to VSSA3 Digital inputs and outputs INPUTS
CMOS level input, high drive, pull-down (pins TEST1, TEST2, TP1 and TP2)
VIL VIH Ci Zi VIL VIH Vhys Ci Zi LOW-level input voltage HIGH-level input voltage input capacitance input impedance - - - - - - - - - 50 - 1.3 - 50 0.3VDDD V - 10 - V pF k 0.7VDDD -
CMOS level input, hysteresis, high drive, pull-up (pin CRESET)
LOW-level input voltage HIGH-level input voltage hysteresis voltage input capacitance input impedance 0.3VDDD V - - 10 - V V pF k 0.7VDDD -
INPUTS/OUTPUTS
I2C-bus level input with Schmitt trigger, open-drain output stage (pins SCL and SDA)
VIL VIH Vhys ILI Ci VOL CL LOW-level input voltage HIGH-level input voltage hysteresis voltage input leakage current input capacitance LOW-level output voltage load capacitance - - - - - - - 0.3VDDD V - 10 10 0.6 400 V V A pF V pF 0.7VDDD - - - - -
0.05VDDD -
TTL/CMOS level, high drive, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS and SDO)
VIL VIH Ci VOL VOH CL Zi OUTPUTS LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage HIGH-level output voltage load capacitance input impedance IOL = 3 mA IOH = -3 mA active pull-up - 2.0 - - 2.4 - - - - - - - - 50 0.8 - 10 0.4 - 100 - V V pF V V pF k
4 mA 3-state output stage (pin SYSCLK)
VOL VOH CL ILO(Z) LOW-level output voltage HIGH-level output voltage load capacitance 3-state leakage current Vi = 0 to VDDD IOL = 2 mA IOH = -2 mA - - - - - - 0.3VDDD V - 100 10 V pF A 0.7VDDD -
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
SYMBOL
PARAMETER
CONDITIONS - - - - - 4 AGCLEV = 0 B/G standard; THD < 1%
MIN.
TYP. - - - - -
MAX.
UNIT
SIF1 and SIF2 analog inputs VSIF(max)(p-p) maximum composite SIF input voltage before clipping (peak-to-peak value) minimum composite SIF input voltage for lower limit of AGC (peak-to-peak value) AGC range input frequency input resistance input capacitance FM deviation FM deviation full-scale level SIF input level adjustment 0 dB SIF input level adjustment -10 dB SIF input level adjustment 0 dB SIF input level adjustment -10 dB 941 2976 59 188 24 - - 7.5 - - mV mV mV mV dB MHz k pF kHz kHz
VSIF(min)(p-p)
AGC fi Ri Ci fFM fFM(FS)
9.2 - 11 - -
10 - 100
terrestrial FM; level 150 adjustment 0 dB; demodulator filter bandwidth set to narrow B/G standard; THD < 1%; 335 demodulator filter bandwidth set to extra wide NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; "CCIR468-2"; quasi peak NN bandwidth = 6 MHz; bit error rate = 10-3; white noise fi = 4 to 9.2 MHz -
fFM(max)
maximum FM deviation in high deviation mode FM carrier-to-noise ratio
-
-
kHz
C/NFM
77
-
dB -----Hz dB -----Hz dB
C/NN
NICAM carrier-to-noise ratio
-
66
-
ct
crosstalk attenuation SIF1 to SIF2
50
-
-
Demodulator performance Vo(nom)(rms) THD + N nominal level output voltage (RMS value) total harmonic distortion plus noise note 1 400 500 0.3 600 0.5 mV %
- from FM source to any output; fi = 1 kHz; bandwidth 20 Hz to 20 kHz; Vo = 1 V (RMS) from NICAM source to any - output; fi = 1 kHz; bandwidth 20 Hz to 20 kHz; Vo = 1 V (RMS)
0.1
0.3
%
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
SYMBOL S/N
PARAMETER signal-to-noise ratio
CONDITIONS Vo = 1 V (RMS); "CCIR468-2"; quasi peak SC1 from FM source to any output SC2 from FM source to any output SC1 during use of high deviation mode from FM source to any output NICAM source
MIN.
TYP.
MAX.
UNIT
64 60 62
70 66 68
- - -
dB dB dB
NICAM in accordance with "EBU specification"; note 2 14.5 14.5 -2 65 40 15 15 - 70 45 - - - +1 - - - kHz kHz dB dB dB dB
B(-3dB)
-3 dB bandwidth
from FM source to any output from NICAM source to any output
fresp cd(dual) cs(stereo) AM
frequency response 20 Hz to 14 kHz dual signal channel separation stereo channel separation AM suppression for FM
from FM/NICAM to any output; reference 1 kHz note 3 note 4
AM: 1 kHz, 30% modulation; 50 reference: fi = 1 kHz; 50 kHz deviation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; "CCIR468-2"; quasi peak 36
dmAM
AM demodulation
45
-
dB
IDENTIFICATION FOR FM SYSTEMS mpilot(ident) C/Npilot(ident) hys(tun) fident pilot modulation for identification pilot sideband C/N for identification start hysteresis identification window B/G stereo slow mode medium mode fast mode B/G dual slow mode medium mode fast mode ton(ident) total identification time on slow mode medium mode fast mode 273.44 272.07 270.73 - - - - - - - - - 274.81 276.20 277.60 2 1 0.5 Hz Hz Hz s s s 116.85 116.11 114.65 - - - 118.12 118.89 120.46 Hz Hz Hz 25 - - 50 27 - 75 - 2 % dB -----Hz dB
1999 Dec 03
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
SYMBOL toff(ident)
PARAMETER total identification time off
CONDITIONS slow mode medium mode fast mode - - - -
MIN. - - -
TYP. 2 1
MAX.
UNIT s s s
0.5 - - 42 - 375 - - 12 70 -
Mono and external inputs Vi(nom)(rms) Vi(cl)(rms) Ri Vo(clip)(rms) Ro RL(AC) RL(DC) Co(L) Voffset(DC) mute nominal level input voltage (RMS value) clipping level input voltage (RMS value) input resistance note 1 THD < 3%; note 5 note 5 500 1400 35 - 250 - - 10 30 - mV mV k
1250 28
Analog audio outputs clipping level output voltage (RMS value) output resistance AC load resistor DC load resistor output load capacitor static DC offset voltage mute suppression nominal input signal from any source; fi = 1 kHz; note 1 from external and mono source; -3 dB bandwidth from any source fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S-bus THD < 3% 1400 150 10 10 - - 80 mV k k nF mV dB
Bline Gro PSRR
bandwidth roll-off gain at 14.5 kHz power supply ripple rejection
20 -3 40
- -2 45
- - -
kHz dB dB
Audio performance THD + N total harmonic distortion plus noise Vin/out = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 20 kHz; from external/mono input to output copy reference voltage V0 = 1.4 V (RMS); fi = 1 kHz; "CCIR468-2"; quasi peak; from external or mono input to output copy between any analog input pairs; fi = 1 kHz between left and right of external input pair between left and right of output pair 1999 Dec 03 21 - 0.1 0.3 %
S/N
signal-to-noise ratio
78
90
-
dB
ct cs
crosstalk attenuation channel separation
70 65 60
- - -
- - -
dB dB dB
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
SYMBOL
PARAMETER
CONDITIONS - - - - CL changed from 18 to 16 pF at nominal frequency - -
MIN.
TYP. - - - 7 -
MAX.
UNIT
Crystal specification (fundamental mode) fxtal CL C1 C0 pull RR RN T XJ XD XA crystal frequency load capacitance series capacitance parallel capacitance pulling sensitivity note 6 24.576 20 20 - 25 - - +25 - - - MHz pF fF pF 10 ----------pF C 10-6 10-6 10 ----------year
-6 -6
equivalent series resistance equivalent series resistance of unwanted mode temperature range adjustment tolerance drift ageing
30 - +70 30 30 5
2RR -20 - across temperature range - -
Notes 1. Definition of levels and level setting: a) The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (FS). b) Nominal audio input levels: external, mono: 500 mV; -9 dB (FS). 2. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to companding, the quantization noise is never lower than -62 dB with respect to the input level. 3. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; Vo = 1 V (RMS) of modulated channel. 4. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; Vo = 1 V (RMS) of modulated channel. 5. If the supply voltage for the TDA9874A is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. 6. The Philips crystal (order number 9922 520 20106) is suitable for this application.
1999 Dec 03
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 6 Level setting FM, AM and NICAM 0 dB (FS) = 1.4 V (RMS); FS = full-scale. SOURCE TRANSMITTER NOMINAL MODULATION DEPTH NOMINAL LEVEL AT DEMODULATOR OUTPUT -24 dB (FS) -19 dB (FS) LEVEL ADJUSTMENT SETTING +9 dB +4 dB NOMINAL LEVEL AT CROSSBAR -15 dB (FS) (spread of 0.5 dB due to different transmitter references) DAC GAIN SETTING +6 dB NOMINAL OUTPUT VOLTAGE VO 500 mV (RMS) 1999 Dec 03 23 Philips Semiconductors
Digital TV sound demodulator/decoder
FM 15 kHz deviation M standard FM B/G, D/K, I standard AM L/L accent standard NICAM B/G, D/K, L standard NICAM I standard 27 kHz deviation
54%
-19 dB (FS)
+4 dB
-11.2 dB (FS)
-18 dB (FS)
+3 dB
-15.8 dB (FS)
-23 dB (FS)
+8 dB
Table 7 Level setting SAT FM 0 dB (FS) = 1.4 V (RMS); FS = full-scale. SOURCE SAT FM stereo SAT FM mono TRANSMITTER MAXIMUM MODULATION DEPTH 50 kHz deviation 85 kHz deviation NOMINAL LEVEL AT DEMODULATOR OUTPUT -13 dB (FS) -9 dB (FS) LEVEL ADJUSTMENT SETTING +4 dB 0 dB MAXIMUM LEVEL AT CROSSBAR -9 dB (FS) DAC GAIN SETTING +6 dB MAXIMUM OUTPUT VOLTAGE VO 1 V (RMS)
Preliminary specification
TDA9874A
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10 I2C-BUS CONTROL 10.1 Introduction 10.2 Power-up state
TDA9874A
The TDA9874A is controlled only via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to let the controlling microprocessor determine whether any action is required. The device has an I2C-bus slave transceiver in accordance with the fast-mode specification with a maximum speed of 400 kbits/s. Information about the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementing functions, there are four possible slave addresses available, which can be selected by pins ADDR1 and ADDR2 (see Table 8). Table 8 ADDR2 0 0 1 1 Possible slave addresses SLAVE ADDRESS ADDR1 A6 0 1 0 1 1 1 1 1 A5 0 0 0 0 A4 1 1 1 1 A3 1 1 1 1 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1
After power-on reset respectively at power-up the device is in the following state: * All outputs muted * No sound carrier frequency loaded * General purpose I/O pins ready for input (HIGH) * Input SIF1 selected with: - AGC on - SIF 10 dB attenuator off - Small hysteresis. * Demodulators for both sound carriers set to FM with: - Identification for B/G, D/K, identification mode `slow' - Level adjustment set to 0 dB - De-emphasis 50 s - Dematrix set to mono - Adaptive de-emphasis off. * Analog outputs are muted and connected to DACs * Digital audio interface all outputs off * Monitor set to carrier 1 DC output. After power-on reset/power-up a device initialization has to be performed via the I2C-bus to put the TDA9874A into the proper mode of operation, in accordance with the desired TV standard, etc. This can be done by writing to all registers with a single I2C-bus transmission (such as a refresh operation) or by writing selectively only to those registers, the contents of which need to be changed with regard to the power-up state. Easy Standard Programming (ESP) can also be used.
The I2C-bus interface remains operational in the standby mode of the TDA9874A to allow the device to be reactivated via the I2C-bus. The device will not respond to a `general call' on the I2C-bus, i.e. when a slave address of 0000 000 is sent by a master.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3 Slave receiver mode
TDA9874A
Commands and data will be processed as soon as they have been received completely. Functions requiring more than one byte will thus be executed only after all bytes for that function have been received. If the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function is ignored. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the level adjustment functions. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. In this case, the last operation will not be executed.
As a slave receiver, the TDA9874A provides 26 registers for storing commands and data. Each register is accessed via a so-called subaddress. A subaddress can be thought of as a pointer to an internal memory location. Detailed descriptions of the slave receiver registers are given in Sections 10.3.2 to 10.3.21. It is allowed to send more than one data byte per transmission to the TDA9874A. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte that is properly stored, is acknowledged with A (acknowledge). If an attempt is made to write data to a non-existing subaddress, the device acknowledges with NA (not acknowledge), therefore telling the I2C-bus master to abort the transmission. There is no `wrap-around' of subaddresses. Table 9 S I2C-bus; slave address/subaddress/data format 0A SUBADDRESS A
SLAVE ADDRESS
DATA
A/NA
P
Table 10 Explanation of Table 9 BIT S SLAVE ADDRESS 0 A SUBADDRESS DATA A/NA P START condition 7-bit device address data direction bit (write to device) acknowledge address of register to write to data byte to be written into register acknowledge or not acknowledge STOP condition FUNCTION
Table 11 Format for a transmission employing auto-increment of subaddresses S SLAVE ADDRESS 0A SUBADDRESS A DATA BYTE A n data bytes with auto-increment of subaddresses DATA A/NA P
10.3.1
PROGRAMMING VIA THE I2C-BUS
The TDA9874A can be programmed in the same way as its predecessor (TDA9874H) using the subaddresses 0 to 24 or by using ESP.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.1.1 Programming via subaddresses 0 to 24
TDA9874A
Subaddress 255 gives control of most standard dependent settings of the IC; see ESP register in Section 10.3.23. When using ESP it is recommended not to write data to subaddresses 3 to 10. A possible programming flow for using ESP and automatic FM dematrixing (TVSM = 1 and IDSWFM = 1) is shown in Table 12. It should be noted that the NICAM configuration register and the level adjustment registers for FM and NICAM are not affected by ESP.
While programming the TDA9874A, by writing to subaddresses 0 to 24, it is not allowed to access subaddress 255. Writing data to subaddress 255 will overwrite the data previously written to subaddresses 3 to 10. This may cause unwanted effects.
10.3.1.2
Using Easy Standard Programming (ESP)
This facility simplifies programming by reducing the amount of data to be set-up and transferred via the I2C-bus.
Table 12 Programming the TDA9874A by using ESP and automatic FM dematrixing REGISTER CONTENT OF REGISTER NUMBER 0 1 NAME AGCCGR GCONR set AGCGR = 20H for using the -10 dB attenuator at the SIF input, otherwise write a 00H to this register select the chosen SIF input pin by writing data to bit SIFSEL (bit 0) and choose the AGC decay time corresponding to your application by writing the appropriate data to bit AGCSLOW (bit 2) set this register according to your sound mode detection algorithm do NOT write data to these registers while using ESP set FMMR = 80H to choose automatic FM dematrixing see Table 38 see Table 39 set NCONR = 04H to select FM source automatically if NICAM is not available see Table 42 set NLELR = 14H (default setting after Power-on reset) if no other value is chosen set NUELR = 50H (default setting after Power-on reset) if no other value is chosen set AMCONR = F9H to enable all analog outputs Set SDACOSR = 81H to select +6 dB gain (see Table 48) and NICAM or FM output. To select an internal source set AOSR = 80H to select dual A or set AOSR = C0H to select dual B (if dual mode is transmitted) to all analog outputs. For selecting an external source see Section 10.3.18. use only for I2S-bus output, see detailed description in Section 10.3.19 use only for I2S-bus output, see detailed description in Section 10.3.20 use only for I2S-bus output, see detailed description in Section 10.3.21
2 3 to 10 11 12 13 14 15 16 17 18 19 20
MSR - FMMR C1OLAR C2OLAR NCONR NOLAR NLELR NUELR AMCONR SDACOSR AOSR
21 22 23 24
DAICONR I2SOSR I2SOLAR
MDACOSR Set MDACOSR = 82H to select dual A or set MDACOSR = 83H to select dual B (if dual mode is transmitted) to all analog outputs. For selecting an external source see Section 10.3.22. ESP see detailed description in Section 10.3.23
255
1999 Dec 03
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 13 Overview of the slave receiver registers 1999 Dec 03 27 Philips Semiconductors
Digital TV sound demodulator/decoder
SUBADDRESS (DECIMAL) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DATA FUNCTION 7 0 P2OUT PEAK B7 B7 B7 B7 B7 B7 IDMOD1 ADEEM2 IDSWFM 0 0 6 0 P1OUT 0 B6 B6 B6 B6 B6 B5 IDMOD0 FMDSC23 0 0 0 5 AGCLEV STDBY 0 B5 B5 B5 B5 B5 B5 IDAREA 4 B4 INIT MCSM1 B4 B4 B4 B4 B4 B4 FILTBW1 3 B3 CLRPFR MCSM0 B3 B3 B3 B3 B3 B3 2 B2 AGCSLOW 0 B2 B2 B2 B2 B2 B2 1 B1 AGCOFF MSS1 B1 B1 B1 B1 B1 B1 FILTBW0 FMDSC12 FDMS1 B1 B1 NDEEM B1 B1 0 B0 SIFSEL MSS0 B0 B0 B0 B0 B0 B0 AGC gain selection (ignored, if AGC on) general configuration monitor select carrier 1 frequency; MS part carrier 1 frequency carrier 1 frequency; LS part carrier 2 frequency; MS part carrier 2 frequency carrier 2 frequency; LS part
CH2MOD1 CH2MOD0 ADEEM1 0 B3 B3 0 B3 B3 FMDSC13 FDMS2 B2 B2 AMSEL B2 B2
CH1MODE demodulator configuration FMDSC11 FM de-emphasis FDMS0 B0 B0 AMUTE B0 B0 FM dematrix channel 1 output level adjustment channel 2 output level adjustment NICAM configuration NICAM output level adjustment
FMDSC22 FMDSC21 0 0 0 0 0 B5 0 B4 B4 DOUTEN B4 B4
DCXOPULL DCXOTEST 0 B7 0 B6
Preliminary specification
NICAM lower error limit
TDA9874A
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Dec 03 28 Philips Semiconductors SUBADDRESS (DECIMAL) 17 18 19 20 21 22 23 24 25 255 DATA FUNCTION 7 B7 1 SDGS1 TVSM 0 TVSMIIS 0 MDGS1 0 FILTBW1 6 B6 MUTI2S 0 CSM2 0 ICSM2 0 0 0 FILTBW0 5 B5 1 AVL1 CSM1 0 ICSM1 0 0 0 IDMOD1 4 B4 1 AVL0 CSM0 SYSCL1 ICSM0 B3 0 0 IDMOD0 3 B3 1 SDGS0 MOS1 SYSCL0 0 B2 MDGS0 0 EPB3 2 B2 0 MOS0 SYSOUT 0 B1 0 0 EPB2 1 B1 SDOS1 SSS1 I2SFORM ISS1 B0 MDOS1 0 EPB1 0 B0 1 SDOS0 SSS0 IS2OUT ISS0 B0 MDOS0 0 EPB0 NICAM upper error limit audio mute control stereo DAC output select analog output select digital audio interface configuration I2S-bus output select I2S-bus output level adjustment mono DAC output select reserved ESP
Digital TV sound demodulator/decoder
MUTSOUT MUTMOUT
Preliminary specification
TDA9874A
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.2 AGC GAIN REGISTER (AGCGR)
TDA9874A
If the Automatic Gain Control (AGC) function is switched off in the general configuration register (see Section 10.3.3) the contents of this register defines a fixed gain of the SIF input stage. The input voltages given are meant to generate a nearly full-scale output from the SIF ADC. If the AGC is on, the AGC gain setting is ignored. After switching off the AGC function, the latest gain control setting is copied to the AGC gain register. If the AGC input level shift bit (AGCLEV) is set to HIGH the input signal is scaled with -10 dB. The AGCLEV bit is also active if the AGC function is enabled. The default setting after power-on reset is `0000 0000'. In Table 16 the stated step number corresponds with the SIF level read from subaddress 7 (see Section 10.4.6); the input voltages should be considered as approximate target values. Table 14 AGC gain register (subaddress 0) 7 0 6 0 5 AGCLEV 4 AGCB4 3 AGCB3 2 AGCB2 1 AGCB1 0 AGCB0
Table 15 Description of the AGCGR bits BIT 7 6 5 4 3 2 1 0 NAME - - AGCLEV AGCB4 AGCB3 AGCB2 AGCB1 AGCB0 DESCRIPTION this bit is not used and should be set to a logic 0 this bit is not used and should be set to a logic 0 If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with -10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 16 AGC gain register 7 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 AGCLEV 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 4 AGCB4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 AGCB3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 AGCB2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 AGCB1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
TDA9874A
AGC GAIN MAX. SIF INPUT (dB) VOLTAGE (mV; RMS) AGCB0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0.0 0.8 1.5 2.3 3.1 3.9 4.6 5.4 6.2 7.0 7.7 8.5 9.3 10.1 10.8 11.6 12.4 13.2 13.9 14.7 15.5 16.3 17.0 17.8 18.6 19.4 20.1 20.9 21.7 22.5 23.2 24.0 333/1052 304/963 278/881 255/806 233/737 213/674 195/617 178/564 163/516 149/472 136/432 125/395 114/361 104/330 96/302 87/276 80/253 73/231 67/212 61/194 56/177 51/162 47/148 43/135 39/124 36/113 33/104 30/95 27/87 25/79 23/73 21/66
0
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.3 GENERAL CONFIGURATION REGISTER (GCONR)
TDA9874A
The default setting after power-on reset is `1100 0000'. Table 17 General configuration register (subaddress 1) 7 P2OUT 6 P1OUT 5 STDBY 4 INIT 3 CLRPFR 2 AGCSLOW 1 AGCOFF 0 SIFSEL
Table 18 Description of the GCONR bits BIT 7 6 SYMBOL P2OUT P1OUT DESCRIPTION General purpose I/O pins 1 and 2: these bits control the general purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If an input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the device status register (see Section 10.4.1). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. Standby mode on/off: when STDBY = 1 the TDA9874A is set to the standby mode. Most functions are disabled and power dissipation is somewhat reduced. When STDBY = 0, the TDA9874A is in its normal mode of operation. On return from standby mode, the device is in its Power-on reset mode and needs to be reinitialized with data defined by the user. Initialize to default settings: when INIT = 1 it causes initialization of TDA9874A to its default settings. This has the same effect as a Power-on reset. In the event of a conflict between the default settings and any bit set HIGH in this register, the bits actually written to this register will overwrite the default settings. This bit is automatically reset to LOW after initialization has been completed. When set LOW, the TDA9874A is in its normal mode of operation. Clear power failure register: when CLRPFR = 1 it resets the clear power failure register. This bit is automatically reset to CLRPFR = 0 after bit PFR in the device status register has been read. AGC decay time: when AGCSLOW = 1 a longer decay time and larger hysteresis are selected for input signals with strong video modulation (conventional intercarrier). This bit has only an effect, when bit AGCOFF = 0. When AGCSLOW = 0, it selects normal attack and decay times for the AGC and a small hysteresis. AGC on/off: when AGCOFF = 1 it forces the AGC block to a fixed gain as defined in the AGC gain register (see Section 10.3.2). When AGCOFF = 0, the AGC function is enabled and the contents of the AGC gain register are ignored. SIF input select: when SIFSEL = 1 it selects pin SIF2 for input (recommended for satellite tuner). When SIFSEL = 0, pin SIF1 (recommended for terrestrial TV) is selected.
5
STDBY
4
INIT
3
CLRPFR
2
AGCSLOW
1
AGCOFF
0
SIFSEL
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.4 MONITOR SELECT REGISTER (MSR)
TDA9874A
This register is used to define the signal source (the level of which is to be monitored) and the signal channel. Data can be monitored e.g. before or after the DC filter at the FM/AM demodulator outputs. The peak level of signals can also be observed. The last available data sample can be read out in the I2C-bus slave transmitter mode (see Section 10.4.5). Phase means the differentiated phase output of the FM demodulator and is provided when the demodulator operates in FM mode. The magnitude is supplied in AM mode. The default setting after power-on reset is `0000 0000'. Table 19 Monitor select register (subaddress 2) 7 PEAK 6 0 5 0 4 MCSM1 3 MCSM0 2 0 1 MSS1 0 MSS0
Table 20 Description of the MSR bits BIT 7 SYMBOL PEAK DESCRIPTION Peak level select: when PEAK = 1 it selects the rectified peak level of a source to be monitored. Peak level value is reset to logic 0 after read-out (see read registers 5 and 6). After changing the monitor signal source for peak calculation it is advisable to ignore the first read-out value due to stored data from previous calculations. these 2 bits are not used and should be set to logic 0 Signal channel select: the state of these 2 bits determine which signal channel is selected; see Table 21. this bit is not used and should be set to logic 0 Signal source select: the state of these 2 bits determine which signal source is selected; see Table 22.
6 5 4 3 2 1 0
- - MCSM1 MCSM0 - MSS1 MSS0
Table 21 Signal channel selection MCSM1 0 0 1 MCSM0 0 1 0 SIGNAL CHANNEL CH1 + CH2 ----------------------------2 CH1 CH2
Table 22 Signal source selection MSS1 0 0 1 1 MSS0 0 1 0 1 SIGNAL SOURCE DC output of FM/AM demodulator magnitude/phase output of FM/AM demodulator FM/AM path output NICAM path output
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.5 CARRIER 1 FREQUENCY REGISTER (C1FR) where: data = 24-bit frequency control word
TDA9874A
This register should not be used when applying ESP. Three bytes are required to define a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency. These three bytes are stored at subaddresses 3 to 5; subaddress 3 being the high byte. Execution of the command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. The sound carrier frequency can be calculated in accordance with the following formula: f mix 24 data = -------- x 2 f clk
fmix = desired sound carrier frequency fclk = 12.288 MHz (clock frequency of mixer) 224 = 16777216 (number of steps in a 24-bit word size). Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9874A (data = 7509333 in decimal notation or 729555 in hexadecimal notation): 01110010 10010101 01010101. The default setting after power-on reset is `0000 0000' for all three bytes.
Table 23 Carrier 1 frequency register high byte (subaddress 3) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
Table 24 Carrier 1 frequency register middle byte (subaddress 4) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
Table 25 Carrier 1 frequency register low byte (subaddress 5) 7 B7 10.3.6 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
CARRIER 2 FREQUENCY REGISTER (C2FR)
This register should not be used when applying ESP. The format is the same as for sound carrier 1, except subaddresses 6 to 8 are used. Subaddress 6 holds the high byte. If the C2FR is used, it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier.
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.7 DEMODULATOR CONFIGURATION REGISTER (DCONR)
TDA9874A
This register should not be used when applying ESP. The default setting after power-on reset is `0000 0000'. Table 26 Demodulator configuration register (subaddress 9) 7 IDMOD1 6 IDMOD0 5 IDAREA 4 FILTBW1 3 CH2MOD1 2 CH2MOD0 1 FILTBW0 0 CH1MODE
Table 27 Description of the DCONR bits BIT 7 6 5 SYMBOL IDMOD1 IDMOD0 IDAREA DESCRIPTION Identification mode for FM sound: these bits define the integrator time of the FM identification. A valid result may be expected after twice this time has expired, at the latest. The longer the time, the more reliable the identification; see Table 28. Application area for FM identification: when IDAREA = 1 it selects the FM identification frequencies in accordance with the specification for Korea. When IDAREA = 0, frequencies for Europe are selected (B/G and D/K standard). selects filter bandwidth in accordance with Table 30 Channel 2 receive mode: these bits control the hardware for the second sound carrier in accordance with Table 29. The NICAM mode employs a wider bandwidth of the decimation filters than the FM mode. selects filter bandwidth in accordance with Table 30 Channel 1 receive mode: when CH1MODE = 1 it selects the hardware for the first sound carrier to operate in AM mode. When CH1MODE = 0 the FM mode is assumed. This applies to both terrestrial and satellite FM reception.
4 3 2 1 0
FILTBW1 CH2MOD1 CH2MOD0 FILTBW0 CH1MODE
Table 28 Identification mode IDMOD1 0 0 1 1 IDMOD0 0 1 0 1 slow medium fast off/reset, recommended during use of high deviation mode IDENTIFICATION MODE
Table 29 Channel 2 receive mode CH2MOD1 0 0 1 CH2MOD0 0 1 0 FM AM NICAM CHANNEL 2
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 30 Filter bandwidth for channel 1 and channel 2; note 1 FILTER BANDWIDTH FILTBW1 0 0 FILTBW0 CHANNEL 1 0 1 narrow extra wide CHANNEL 2 narrow narrow FILTER MODES
TDA9874A
Recommended for nominal terrestrial broadcast conditions and SAT with 2 carriers Recommended for highly overmodulated single FM carriers. Only channel 1 is available for FM demodulation in this mode. NICAM can still be processed on channel 2. Recommended for moderately overmodulated broadcast conditions Recommended for strongly overmodulated broadcast conditions
1 1 Note
0 1
medium wide
medium wide
1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. Switching the identification off will reset the associated hardware to a defined state. 10.3.8 FM DE-EMPHASIS REGISTER (FMDR)
This register should not be used when applying ESP. This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits 3 to 0 apply to sound carrier 1, bits 7 to 4 apply to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics. The default setting after power-on reset is `0000 0000'. Table 31 FM De-emphasis register (subaddress 10) 7 ADEEM2 6 FMDSC23 5 FMDSC22 4 FMDSC21 3 ADEEM1 2 FMDSC13 1 FMDSC12 0 FMDSC11
Table 32 Description of the FMDR bits BIT 7 SYMBOL ADEEM2 DESCRIPTION Adaptive de-emphasis on/off sound carrier 2: when ADEEM2 = 1 it activates the adaptive de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. When ADEEM2 = 0, the adaptive de-emphasis is off. FM de-emphasis: the state of these 3 bits determines the FM de-emphasis for sound carrier 2; see Table 33.
6 5 4 3
FMDSC23 FMDSC22 FMDSC21 ADEEM1
Adaptive de-emphasis on/off sound carrier 1: when ADEEM1 = 1 it activates the adaptive de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. When ADEEM1 = 0, the adaptive de-emphasis is off. FM de-emphasis: the state of these 3 bits determines the FM de-emphasis for sound carrier 1; see Table 33.
2 1 0
FMDSC13 FMDSC12 FMDSC11
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 33 De-emphasis FMDSC23; FMDSC13 0 0 0 0 1 Notes 1. The FM de-emphasis gain is 0 dB at 40 Hz. FMDSC22; FMDSC12 0 0 1 1 0 FMDSC21;FMDSC11 0 1 0 1 0
TDA9874A
DE-EMPHASIS(1) 50 s 60 s 75 s J17(2) off
2. Not used in any known terrestrial TV sound standard. NICAM de-emphasis is selected in the NICAM configuration register; see Table 41. 10.3.9 FM DEMATRIX REGISTER (FMMR)
This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. For the dematrixing, it is assumed that the output from sound carrier 1 is on channel 1 input. Bits 3 to 6 are not used. The default setting after power-on reset is `0000 0000'. Table 34 FM dematrix register (subaddress 11) 7 IDSWFM 6 0 5 0 4 0 3 0 2 FDMS2 1 FDMS1 0 FDMS0
Table 35 Description of the FMMR bits BIT 7 SYMBOL IDSWFM DESCRIPTION Automatic FM-dematrix switching: if set to logic 1, the FM dematrix is switched automatically in dependence on the current FM identification result. In case of stereo, the type of stereo dematrixing (Europe or Korea) is determined by bit IDAREA in subaddress 9. Bits FDMS2, FDMS1 and FDMS0 are ignored and the dematrix output is set according to Table 37. With channel 2 in NICAM mode, mono (channel 1) is always selected. these 4 bits are not used and should be set to logic 0
6 5 4 3 2 1 0
- - - - FDMS2 FDMS1 FDMS0
Dematrixing characteristics select: the state of these 3 bits select the dematrixing characteristics; see Table 36
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Preliminary specification
Digital TV sound demodulator/decoder
Table 36 Selection of the dematrixing characteristics (manual mode) FDMS2 0 0 0 0 1 1 1 FDMS1 0 0 1 1 0 0 1 FDMS0 0 1 0 1 0 1 0 L OUTPUT CH1 CH2 CH1 CH2 2CH1 - CH2 CH1 + CH2 ----------------------------2 CH1 + CH2 R OUTPUT CH1 CH2 CH2 CH1 CH2 CH1 - CH2 ----------------------------2 CH1 - CH2
TDA9874A
MODE mono 1 mono 2 dual dual swapped stereo Europe stereo Korea -6 dB stereo Korea
Table 37 Setting of the dematrixing characteristics (automatic mode) IDENTIFICATION MODE Mono Stereo Dual Europe Korea L OUTPUT CH1 2CH1 - CH2 CH1 + CH2 CH1 R OUTPUT CH1 CH2 CH1 - CH2 CH2
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.10 CHANNEL 1 OUTPUT LEVEL ADJUSTMENT REGISTER (C1OLAR)
TDA9874A
This register is used to correct for standard and station-dependent differences of signal levels. Table 38 applies to the FM dematrix output channel 1. The default setting after power-on reset is `0000 0000'. Table 38 Channel 1 output level adjustment register (subaddress 12) The selected gain is also applied to the FM signal channel 1 for input to the mono channel. 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.11 CHANNEL 2 OUTPUT LEVEL ADJUSTMENT REGISTER (C2OLAR)
TDA9874A
This register is used to correct for standard and station-dependent differences of signal levels. Table 39 applies to the FM dematrix output channel 2 in its FM and AM modes. In the event of FM stereo or FM dual language reception, channels 1 and 2 should be adjusted to the same level. The default setting after power-on reset is `0000 0000'. Table 39 Channel 2 output level adjustment register (subaddress 13) The gain chosen is also applied to the FM signal channel 1 for input to the mono channel. 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.12 NICAM CONFIGURATION REGISTER (NCONR) The default setting after power-on reset is `0000 0000'. Table 40 NICAM configuration register (subaddress 14) 7 DCXOPULL 6 DCXOTEST 5 0 4 DOUTEN 3 0 2 AMSEL 1
TDA9874A
0 AMUTE
NDEEM
Table 41 Description of the NCONR bits; see notes 1 to 4 BIT 7 SYMBOL DESCRIPTION
DCXOPULL DCXO frequency select: selects DCXO lower or upper test frequency during DCXO test mode. When DCXOPULL = 1 it sets the DCXO to the lower DCXO frequency. When DCXOPULL = 0 it sets the DCXO to its higher frequency. DCXOTEST DCXO test mode enable: when DCXOTEST = 1 it enables the DCXO test mode (available only during FM mode). In this mode frequency pulling via DCXOPULL is enabled. When DCXOTEST = 0 it enables normal operation. - DOUTEN this bit is not used and should be set to logic 0 Data output enable: when DOUTEN = 1 it enables the output of the NICAM serial data stream from the DQPSK demodulator and of the associated clock, PCLK. When DOUTEN = 0, both outputs will be 3-stated. this bit is not used and should be set to logic 0 Auto-mute select: when AMSEL = 1 the auto-mute will switch between NICAM sound and the analog mono input. This bit only has an effect when the auto-mute function is enabled and when the DAC has been selected in the analog output select register (see Section 10.3.18). When AMSEL = 0, the auto-mute will switch between NICAM sound and the sound on the first sound carrier (i.e. FM mono or AM). De-emphasis on/off: when NDEEM = 1 it switches the NICAM J17 de-emphasis off. When NDEEM = 0 it switches the NICAM J17 de-emphasis on. Auto-muting on/off: when AMUTE = 1 automatic muting is disabled. This bit only has an effect when the second sound carrier is set to NICAM. When AMUTE = 0 it enables the automatic switching between NICAM and the program on the first sound carrier (i.e. FM mono or AM), depending on the NICAM bit error rate. The FM dematrix should be set to the mono position or IDSWFM (subaddress 11) should be set.
6
5 4
3 2
- AMSEL
1 0
NDEEM AMUTE
Notes 1. The decision of whether auto-muting is permitted will be taken by the controlling microprocessor based on information contained in the TDA9874A's status registers. Thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with "NICAM 728 ETS Revised for Data Applications" or any other preference. 2. The NICAM de-emphasis gain is 0 dB at 40 Hz. 3. The AMSEL bit has only an effect on the analog sound outputs (OUTL, OUTR and OUTM). With regard to the digital sound output (I2S-bus), the auto-mute will only switch between NICAM and the first sound carrier. 4. The DCXO test mode is intended for checking the DCXO control range with the actually used PCB layout and crystal type. During normal operation, the DCXO test mode should not be used.
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.13 NICAM OUTPUT LEVEL ADJUSTMENT REGISTER (NOLAR)
TDA9874A
This register is used to correct for standard and station-dependent differences of signal levels. Table 42 applies to both NICAM sound outputs. The default setting after power-on reset is `0000 0000'. Table 42 NICAM output level adjustment register (subaddress 15) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.14 NICAM LOWER ERROR LIMIT REGISTER (NLELR) When the auto-mute function is enabled (see Section 10.3.12) and the NICAM bit error count is lower than the value contained in this register, the NICAM signal is selected (again) for reproduction; see also Section 10.3.15. The default setting after power-on reset is `0001 0100'. Table 43 NICAM lower error limit register (subaddress 16) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
TDA9874A
The difference between the upper and lower error limit constitutes a hysteresis to avoid frequent switching between NICAM and the program on the 1st sound carrier. The default setting after power-on reset is `0101 0000'. Table 44 NICAM upper error limit register (subaddress 17) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
10.3.16 AUDIO MUTE CONTROL REGISTER (AMCONR) Only bits 6, 2 and 1 are used. The state of the unused bits should be set to logic 1. When any of these bits is set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. The default setting after power-on reset is `1111 1111'.
10.3.15 NICAM UPPER ERROR LIMIT REGISTER (NUELR) When the auto-mute function is enabled (see Section 10.3.12) and the NICAM bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. FM mono or AM sound) or the analog mono input is selected for reproduction. Table 45 Audio mute control register (subaddress 18) 7 1 6 MUTI2S 5 1 4 1
3 1
2 MUTSOUT
1 MUTMOUT
0 1
Table 46 Description of the AMCONR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - MUTI2S - - - MUTSOUT MUTMOUT - Mute Stereo Output: if MUTSOUT = 1 the analog stereo output is muted Mute Mono Output: if MUTMOUT = 1 the analog mono output is muted this bit is not used and should be set to logic 1 DESCRIPTION this bit is not used and should be set to logic 1 Mute I2S-bus output: when MUTI2S = 1 it mutes the I2S-bus output these 3 bits are not used and should be set to logic 1
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Preliminary specification
Digital TV sound demodulator/decoder
10.3.17 STEREO DAC OUTPUT SELECT REGISTER (SDACOSR) This register is used to define the signal source to be entered into the DAC. The stereo DAC output can be routed to the analog stereo output pins, depending on the setting in the AOSR; see Section 10.3.18. A simplified setting is possible, if automatic FM dematrix switching (see Section 10.3.9) and auto-select (see Section 10.3.18) is applied. The two combinations of FM and NICAM shown in Table 50 apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for special applications. It should be noted that the controlling microprocessor has to assure that the FM dematrix is set to the mono position or that IDSWFM is set HIGH. An additional Automatic Volume Level (AVL) control function is implemented, which provides a constant output level of -23 dB (FS) for input levels between 0 and -29 dB (FS). There are some fixed decay time constants to choose from, i.e. 2, 4 or 8 s. The automatic stereo DAC switching, operating similar to the mono DAC switching, is shown in Table 56. The default setting after power-on reset is `0000 0000'. Bits 2 and 6 are not used and should be set to logic 0. Table 47 Stereo DAC output select register (subaddress 19) 7 6 5 AVL 1 4 AVL 0 3 2 1 0 Table 49 AVL control mode The AVL attack time is always 10 ms. AVL1 0 0 1 1 AVL0 0 1 0 1 off or reset
TDA9874A
AVL MODE short decay (2 s) medium decay (4 s) long decay (8 s)
Table 50 Signal source left and right SIGNAL SOURCE STEREO DAC LEFT 0 0 1 1 0 1 0 1 FM/AM NICAM left FM/AM FM/AM RIGHT FM/AM NICAM right NICAM M1 NICAM M2
SDOS1
SDOS0
The auto-select function is available only if SDOS1 and SDOS0 are set to `00' or `01'. Matrixing can be set in the analog output select register. 10.3.18 ANALOG OUTPUT SELECT REGISTER (AOSR) This register is used to define both the signal source to be output at the analog outputs and the output channel selector mode. The DAC outputs are automatically muted in the event that one of the analog inputs is selected for output. L+R The ------------- position of the matrix applies only to the DAC 2 outputs, it is not available for analog input signals. The default setting after power-on reset is `0000 0000'.
SDGS1 0
SDGS0 0 SDOS1 SDOS0
Table 48 Selection of stereo DAC gain SDGS1 0 0 1 1 SDGS0 0 1 0 1 DAC GAIN (dB) 0 3 6 9
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 51 Analog output select register (subaddress 20) 7 TVSM 6 CSM2 5 CSM1 4 CSM0 3 MOS1 2 MOS0 1 SSS1
TDA9874A
0 SSS0
Table 52 Description of the AOSR bits BIT 7 SYMBOL TVSM DESCRIPTION Auto-select function: for TV applications, only in combination with IDSWFM set HIGH. If set HIGH switches the matrix automatically depending on the IDSTE, IDDUA bits for FM and the S/MB, D/SB bits for NICAM (see Sections 10.4.1 and 10.4.2). Output channel selection mode, stereo output: these 3 bits select the output channel selection mode; see Table 53
6 5 4 3 2 1 0
CSM2 CSM1 CSM0 MOS1 MOS0 SSS1 SSS0
Signal source for mono output: these 2 bits select the signal source for the mono output; see Table 54 Signal source for stereo output: these 2 bits select the signal source for the stereo output; see Table 55
Table 53 Output channel selection mode for stereo output (TVSM = LOW) CSM2 0 0 0 0 1 CSM1 0 0 1 1 0 CSM0 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 - - - - not allowed during use of high deviation mode REMARK
Table 54 Signal source selection analog mono output MOS1 0 0 1 1 Table 55 Signal source selection stereo output SSS1 0 0 1 1 SSS0 0 1 0 1 DAC reserved external input mono input SIGNAL SOURCE MOS0 0 1 0 1 SIGNAL SOURCE mono DAC external input L external input R mono input
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Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
Table 56 Auto-select function (TVSM = HIGH and IDSWFM = HIGH): FM mode/NICAM mode for stereo DAC OUTPUT CHANNEL SELECTION MODE CSM2 0 0 Note 1. X = don't care. Signal source selection bits SDOS1 and SDOS0 must be set to 0X for FM mode (including FM mode by switching if auto-mute select is set LOW) or 01 for NICAM mode, when using the auto-select function. 10.3.19 DIGITAL AUDIO INTERFACE CONFIGURATION REGISTER (DAICONR) The default setting after Power-on reset is 00000000. Table 57 Digital Audio Interface Configuration Register (subaddress 21) 7 0 6 0 5 0 4 SYSCL1 3 SYSCL0 2 SYSOUT 1 I2SFORM 0 I2SOUT CSM1 0 1 CSM0 X(1) 0 FM IDENT/NICAM SOUND MODE MONO M/M M/M STEREO L/R L/R DUAL A/A B/B FM/AM: M/M FM/AM: M/M AUTO-MUTE = HIGH AND CH2MOD = 10
Table 58 Description of the DAICONR bits BIT 7 6 5 4 3 2 SYMBOL - - - SYSCL1 SYSCL0 SYSOUT System clock frequency select: these 2 bits select the frequency of the system clock; see Table 59 System clock output on/off: when SYSOUT = 1 it enables the output of a system (or master) clock signal at pin SYSCLK. When SYSOUT = 0, the output will be off, thereby improving EMC performance. Serial output format: when I2SFORM = 1 it selects an MSB-aligned, MSB-first output format, i.e. a level change at the word select pin indicates the beginning of a new audio sample. When I2SFORM = 0, it selects the standard I2S-bus output format. I2S-bus output on/off: when I2SOUT = 1 it enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9874A then is an I2S-bus master. When I2SOUT = 0, the outputs mentioned will be 3-stated, thereby improving EMC performance. DESCRIPTION these 3 bits are not used and should be set to logic 0
1
I2SFORM
0
I2SOUT
Table 59 System clock frequency select SYSCL1 0 0 1 1 1999 Dec 03 SYSCL0 0 1 0 1 45 SYSCLK OUTPUT 256fs 384fs 512fs 768fs FREQUENCY (MHz) 8.192 12.288 16.384 24.576
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.20 I2S-BUS OUTPUT SELECT REGISTER (I2SOSR)
TDA9874A
This register is used to define both the signal source to be output at the I2S-bus port and the mode of the digital matrix for signal selection. The two combinations of FM and NICAM shown in Table 62 apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for special applications. It should be noted that the controlling microprocessor has to assure that the FM dematrix is set to the mono position or IDSWFM is set HIGH. If the I2S-bus signal source is set to FM left or FM right it is influenced by the automatic FM dematrix switching (see subaddress 11). The default setting after power-on reset is `0000 0000'. Table 60 I2S-bus output select register (subaddress 22) 7 TVSMIIS 6 ICSM2 5 ICSM1 4 ICSM0 3 0 2 0 1 ISS1 0 ISS0
Table 61 Description of the I2SOSR bits BIT 7 SYMBOL TVSMIIS DESCRIPTION Auto-select function: for TV applications, only in combination with IDSWFM set HIGH. If set HIGH switches the matrix automatically depending on the IDSTE, IDDUA bits for FM and the S/MB, D/SB bits for NICAM in transmitters subaddresses 0 and 1 (see Sections 10.4.1 and 10.4.2). Output channel selection mode: these 3 bits select the output channel selection mode; see Table 62
6 5 4 3 2 1 0
ICSM2 ICSM1 ICSM0 - - ISS1 ISS0
these 2 bits are not used and should be set to logic 0 Signal source: these 2 bits select the signal source; see Table 62
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 62 Mode of the digital matrix for signal selection (TVSMIIS = LOW) ICSM2 0 0 0 0 1 ICSM1 0 0 1 1 0 ICSM0 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2
TDA9874A
REMARK - - - - not allowed during use of high deviation mode
Table 63 Signal source left and right; note 1 SIGNAL SOURCE I2S-BUS OUTPUT ISS1 0 0 1 1 Note 1. The auto-select function is available only if ISS1 and ISS0 are set to `00' or `01'. Table 64 Auto-select function (TVSMIIS = HIGH and IDSWFM = HIGH): FM mode/NICAM mode for I2S-bus output I2S-BUS OUTPUT ICSM2 0 0 Note 1. X = don't care. ICSM1 0 1 ICSM0 X(1) 0 FM IDENT/NICAM SOUND MODE MONO M/M M/M STEREO L/R L/R DUAL A/A B/B AUTO-MUTE = HIGH AND CH2MOD = 10 FM/AM: M/M FM/AM: M/M ISS0 LEFT 0 1 0 1 FM/AM left NICAM left FM/AM FM/AM RIGHT FM/AM right NICAM right NICAM M1 NICAM M2
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.21 I2S-BUS OUTPUT LEVEL ADJUSTMENT REGISTER (I2SOLAR)
TDA9874A
This register is used to adjust the output level at the I2S-bus port. Left and right signal channels are treated identically. The default setting after power-on reset is `0000 0000'. Table 65 I2S-bus output level adjustment register (subaddress 23) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.22 MONO DAC OUTPUT SELECT REGISTER (MDACOSR) This register is used to define the signal source to be entered into the mono DAC. The mono DAC is used for signal output from digital sources. For the mono DAC output auto-matrix switching is always active. L+R In stereo mode ------------- is chosen automatically. Selecting 2 Language B (MDOS1, MDOS0 = 01 or 11) will only show effect, while a dual transmission via FM A2 or NICAM is being received. Settings in the FM dematrix register have no effect on the source selection for the mono DAC. Table 66 Mono DAC output select register (subaddress 24) 7 MDGS1 6 0 5 0 4 0 3 MDGS0 2 0 1
TDA9874A
The level adjustment for an FM source is determined by the Channel 1 output level adjustment register (subaddress 12) for mono/dual A, or by the Channel 2 output level adjustment register (subaddress 13) for dual B, or by the NICAM output level adjustment register (subaddress 15) if a NICAM source is selected. Some extra gain can be introduced at the input to the DAC to provide a coarse level adjustment function. The default setting after power-on reset is `0000 0000'. Bits 2, 4, 5 and 6 are don't care and should be set to logic 0.
0 MDOS0
MDOS1
Table 67 Selection of DAC gain MDGS1 0 0 1 1 Table 68 Signal source MDOS1 0 0 1 1 MDOS0 0 1 0 1 MONO DAC OUTPUT L+R FM/AM ------------- or mono/dual A 2 FM/AM dual B if dual mode transmission, otherwise mono L+R NICAM ------------- or mono/dual A 2 NICAM mono 2 if dual mode transmission, otherwise mono MDGS0 0 1 0 1 DAC GAIN (dB) 0 3 6 9
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.3.23 EASY STANDARD PROGRAMMING (ESP) REGISTER This register is used to simplify the setting of different TV sound standards via the I2C-bus. Writing to this register will overwrite the contents of registers 3 to 10 with the settings needed to demodulate one of the standards shown in Table 70. After power-up, the default setting has no effect on the settings of registers 3 to 10. Old values of registers 3 to 10 are not stored. Demodulators filter the bandwidth and identification time constants are also set independently from the chosen standard selected in this register. This means for I2C-bus refreshing: using the ESP option, registers 3 to 10 should not be overwritten during a refresh.
TDA9874A
If ESP is not used, the ESP register should not be accessed in the refresh routine. Demodulators filter bandwidth and identification time constants are also set independently in this register. The default setting after power-on reset is `0000 0000'. For a description of bits IDMOD0 and IDMOD1 (FM identification mode), FILTBW0 and FILTBW1 (demodulator filter bandwidth) refer to Section 10.3.7. Bits IDMOD0 and IDMOD1 (FM identification mode), FILTBW0 and FILTBW1 (demodulator filter bandwidth) are identical in registers 255 and 9.
Table 69 Easy standard programming register (subaddress 255) 7 FILTBW1 6 FILTBW0 5 IDMOD1 4 IDMOD0 3 EPB3 2 EPB2 1 EPB1 0 EPB0
Table 70 Available standards for easy standard programming STANDARD EPB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 EPB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 EPB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 EPB0 NUMBER 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAME A2, B/G A2, M (Korea) A2, D/K (1) A2, D/K (2) A2, D/K (3) NICAM, I NICAM, B/G NICAM, D/K NICAM, L reserved reserved reserved Astra satellite stereo (7.02/7.20 MHz) reserved reserved reserved
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.4 Slave transmitter mode
TDA9874A
As a slave transmitter, the TDA9874A provides 12 registers with status information and data, a part of which is for Philips internal purposes only. Each register is accessed by means of a subaddress. Detailed descriptions of the slave transmitter registers are given in Sections 10.4.1 to 10.4.9. Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9874A. In this case, the subaddress is automatically incremented after each data byte, resulting in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Each data byte in a read sequence, except for the last one, is acknowledged with Am. The subaddresses `wrap around' from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation. Table 71 General format for reading data from the TDA9874A S SLAVE ADDRESS 0 A SUBADDRESS A Sr SLAVE ADDRESS 1 A Table 72 Explanation of Tables 71 and 73 BIT S SLAVE ADDRESS 0 A SUBADDRESS Sr 1 DATA NAm Am P START condition 7-bit device address data direction bit (write to device) acknowledge (by the slave) address of register to read from repeated START condition data direction bit (read from device) data byte read from register not acknowledge (by the master) acknowledge (by the master) STOP condition FUNCTION DATA NAm P
Table 73 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 A SUBADDRESS A Sr SLAVE ADDRESS 1 A DATA BYTE Am DATA NAm P n data bytes with auto-increment of subaddresses
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 74 Overview of the slave transmitter registers 1999 Dec 03 52 Philips Semiconductors
Digital TV sound demodulator/decoder
SUBADDRESS (DECIMAL)(1) 0 1 2 3 4 5 6 7 252 253 254 255 Note
DATA FUNCTION 7 P2IN C4 B7 AD7 OVW B7 B7 IDPILOT B7 B7 B7 B7 6 P1IN C3 B6 AD6 SAD B6 B6 - B6 B6 B6 B6 5 RSSF C2 B5 AD5 - B5 B5 - B5 B5 B5 B5 4 AMSTAT C1 B4 AD4 CI1 B4 B4 B4 B4 B4 B4 B4 3 VDSP OSB B3 AD3 CI2 B3 B3 B3 B3 B3 B3 B3 2 IDDUA CFC B2 AD2 AD10 B2 B2 B2 B2 B2 B2 B2 1 IDSTE S/MB B1 AD1 AD9 B1 B1 B1 B1 B1 B1 B1 0 PFR D/SB B0 AD0 AD8 B0 B0 B0 B0 B0 B0 B0 device status (identification, etc.) NICAM status NICAM error count additional data (LSB) additional data (MSB) level read-out (MSB) level read-out (LSB) SIF level test register 2 test register 1 device identification code software identification code
1. Registers from subaddress 252 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices.
Preliminary specification
TDA9874A
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.4.1 DEVICE STATUS REGISTER (DSR)
TDA9874A
Table 75 Device status register (subaddress 0) 7 P2IN 6 P1IN 5 RSSF 4 AMSTAT 3 VDSP 2 IDDUA 1 IDSTE 0 PFR
Table 76 Description of the DSR bits BIT 7 SYMBOL P2IN DESCRIPTION Input from Port 2: this bit reflects the status of the P2 general purpose port pin; see Section 10.3.3. If P2IN = 1, then the P2 general purpose port pin is HIGH. If P2IN = 0, then the P2 general purpose port pin is LOW. Input from Port 1: this bit reflects the status of the P1 general purpose port pin; see Section 10.3.3. If P1IN = 1, then the P1 general purpose port pin is HIGH. If P1IN = 0, then the P1 general purpose port pin is LOW. Reserve Sound Switching Flag: when RSSF = 1, this bit is a copy of the C4 bit in the NICAM status register (see Section 10.4.2). It indicates that the FM (or AM for standard L) sound matches the digital transmission and auto-muting should be enabled. When RSSF = 0, auto-muting should be disabled, as analog and digital sound are different. Auto-mute Status: if this bit is HIGH, it indicates that the auto-muting function has switched from NICAM to the program of the first sound carrier (i.e. FM mono or AM in NICAM L systems) Identification of NICAM sound: when VDSP = 1, it indicates that digital transmission is a sound source. When VDSP = 0, it indicates that the transmission is either data or a currently undefined format. Identification of FM dual sound; A2 systems: if IDDUA = 1, an FM dual-language signal has been identified. When neither IDSTE nor IDDUA = 1, the received signal is assumed to be FM mono (A2 systems only). Identification of FM stereo; A2 systems: if IDSTE = 1, an FM stereo signal has been identified (A2 systems only) Power failure register: the power supply for the digital part of the device (VDDD1) has temporarily been lower than the specified lower limit. If this is detected an initialization of the device has to be carried out to ensure reliable operation.
6
P1IN
5
RSSF
4
AMSTAT
3
VDSP
2
IDDUA
1 0
IDSTE PFR
10.4.2
NICAM STATUS REGISTER (NISR)
Table 77 NICAM status register (subaddress 1) 7 C4 6 C3 5 C2 4 C1 3 OSB 2 CFC 1 S/MB 0 D/SB
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 78 Description of the NISR bits; notes 1 and 2 BIT 7 6 5 4 3 SYMBOL C4 C3 C2 C1 OSB DESCRIPTION
TDA9874A
NICAM application control bits: these bits correspond to the control bits C1 to C4 in the NICAM transmission.
Synchronization bit: when OSB = 1, it indicates that the device has both frame and C0 (16 frame) synchronization. When OSB = 0, it indicates that the audio output from the NICAM part is digital silence. Configuration change: when CFC = 1, it indicates a configuration change at the 16 frame (C0) boundary Identification of NICAM stereo: when S/MB = 1, it indicates stereo mode Identification of NICAM dual mono: when D/SB = 1, it indicates dual mono mode.
2 1 0 Notes
CFC S/MB D/SB
1. The TDA9874A does not support the extended control modes. Therefore, the program of the first sound carrier (i.e. FM mono or AM) is selected for reproduction in case bit C3 is set HIGH, independent of bit AMUTE in the NICAM configuration register being set or not. 2. When a NICAM transmitter is switched off, the device will lose synchronization. In that case the program of the first sound carrier is selected for reproduction, independent of bit AMUTE being set or not. 10.4.3 NICAM ERROR COUNT REGISTER (NIECR)
Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms. Table 79 NICAM error count register (subaddress 2) 7 B7 10.4.4 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
DATA REGISTERS (DR1 AND DR2)
The contents of these two registers provide information on the additional data bits. AD byte 0 is stored at subaddress 3. Table 80 Data register 1 (subaddress 3) 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
Table 81 Description of the DR1 bits BIT 7 to 0 SYMBOL AD7 to AD0 DESCRIPTION The lower 8 bits of the additional data word.
Table 82 Data register 2 (subaddress 4) 7 OVW 6 SAD 5 - 4 CI1 3 CI2 2 AD10 1 AD9 0 AD8
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
Table 83 Description of the DR2 bits BIT 7 6 5 4 3 2 1 0 10.4.5 SYMBOL OVW SAD - CI1 CI2 AD10 AD9 AD8 LEVEL READ-OUT REGISTERS (LRRA AND LRRB) DESCRIPTION
TDA9874A
If this bit is HIGH, new additional data bits are written to the IC without the previous bits being read. When SAD = 1, new additional data is written into the IC. This bit is reset when the additional data bits are read. this bit is undefined These 2 bits are CI bits decoded by majority logic from the parity checks of the last ten samples in a frame. the upper 3 bits of the additional data word
Table 86 SIF level register (subaddress 7) 7 IDPILOT 6 - 5 - 4 B4 3 B3 2 B2 1 B1 0 B0
These two bytes constitute a word that provides data from a location that has been specified with the monitor select register (see Section 10.3.4). The most significant byte of the data is stored at subaddress 5. Table 84 Level read-out register A (subaddress 5) 7 B7(1) Note 1. B7 is the most significant bit or sign bit of the word. Table 85 Level read-out register B (subaddress 6) 7 B7 Note 1. B0 is the least significant bit of the word. 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0(1) 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
Table 87 Description of the SIF level bits BIT 7 SYMBOL IDPILOT DESCRIPTION IDPILOT bit: when IDPILOT = 1 it indicates that an FM pilot carrier in the 2nd channel is detected; note 1 this bit is undefined this bit is undefined SIF level data bits: these bits correspond to the input level at the selected SIF input
6 5 4 3 2 1 0 Note
- - B4 B3 B2 B1 B0
10.4.6
SIF LEVEL REGISTER (SIFLR)
When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number can be interpreted in the same way as the AGC gain register setting (see Section 10.3.2), i.e. if the SIF AGC were set to a fixed gain and the same number loaded into the AGC gain register, the current SIF input signal level would generate a SIF ADC output close to full-scale. When the SIF AGC is off, this register returns the contents of the AGC gain register. Bits B5 and B6 are don't care.
1. The pilot detector is faster than the stereo/dual identification, but not as reliable and slightly less sensitive. By means of the pilot detector bit, the control software is able to identify an analog 2-carrier (A2) standard transmission within approximately 0.1 s and even in the event of a mono transmission (second sound carrier with pilot). Certain NICAM test signals may trigger a wrong pilot indication, therefore the pilot detector bit should not be evaluated at channel 2 mixer frequencies that correspond to NICAM carriers (5.85 and 6.552 MHz). For detailed information, please contact a Philips representative.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
10.4.7 TEST REGISTER 2 (TR2) 11 I2S-BUS DESCRIPTION
TDA9874A
This register contains, as a binary number, the highest subaddress used for slave receiver registers. The first version will have the identification `0010 1101'. Table 88 Test register 2 (subaddress 252) 7 B7 10.4.8 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
The digital audio interface of the TDA9874A consists of a serial audio output and associated clock signals. It can be used to supply digital audio signals from received TV programs to a suitable output device, e.g. a DAC or an AES/EBU transmitter. Two serial audio formats are supported at the digital audio interface, the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.8. In both formats the left audio channel of a stereo sample pair is output first, and is on the Serial Data line (SDO) when the Word Select line (WS) is LOW. Data is written on the trailing edge of SCK and read on the leading edge of SCK. The most significant bit is sent first. After power-on reset, the outputs of the digital audio interface are 3-stated to reduce EMC and allow for combinations with other ICs. If an output is desired, it has to be activated by means of an I2C-bus command. When the output is enabled, serial audio data can be taken from pin SDO. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language. The Word Select output (WS) is clocked with the audio sample frequency of 32 kHz. The Serial Clock output (SCK) is clocked at a frequency of 2.048 MHz. This means that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. There are 18 significant bits used on the Serial Data Output (SDO). A symmetrical system clock output (SYSCLK) is available from the TDA9874A as a master clock for external digital audio devices. After Power-on reset, the clock is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz.
TEST REGISTER 1 (TR1)
This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. The first version will have the identification `0000 0111'. Table 89 Test register 1 (subaddress 253) 7 B7 10.4.9 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
DEVICE IDENTIFICATION CODE (DIC)
There will be several devices in the digital TV sound processor family, with TDA9874A being the second member. This byte is used to identify the individual family members. The first version will have the identification `0001 0001'. Table 90 Device identification code (subaddress 254) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
10.4.10 SOFTWARE IDENTIFICATION CODE (SIC) It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g. to incorporate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases. The first version will have the identification `0000 0010'. Table 91 Software identification code (subaddress 255) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
handbook, full pagewidth
SCK
WS
SDO
LSB
MSB
LSB
MSB
MGK759
one sample
a. MSB-aligned format.
handbook, full pagewidth
SCK
WS
SDO
LSB
MSB
LSB
MSB
MGK758
one sample
b. I2S-bus format.
Fig.8 Serial audio interface formats.
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
12 EXTERNAL COMPONENTS
handbook, full pagewidth
470 nF MONOIN 470 nF 470 nF EXTIL 2 41 P1
TDA9874A
EXTIR
1
42
47 F
Vref2
3
40
VSSD3 Lx (2) 470 nF 3.3 SYSCLK +5 V
P2 2.2 F 10 nF
4
39
VDDD3
OUTM
5
38
VSSA4
6
37
SCK
2.2 F 10 nF
OUTL
7
36
WS
I2S-bus
2.2 F
OUTR 10 nF VDDA1 470 nF V SSA1
8
35
SDO
+5 V
10
9
34
SDA I2C-bus
10
33
SCL
VSSD1 470 nF +5 V Lx (2) VSSD2
11
TDA9874APS
32
VDDA3
10 470 nF
+5 V
VDDD1
12
31
VSSA3 1 F
13
30
CRESET
TP2
(1)
SIF1 14 29 Vref1
47 pF
100 nF
50
NICAM
15
28
TP1
(1)
SIF2 16 27 TEST1 17 26 VDEC
47 pF
PCLK
50
(1)
ADDR1
18
25
decoupling capacitor 470 nF
XTALO 24.576 MHz
VSSA2 19 24 ADDR2
XTALI
20
23
TEST2
(1)
21
22
MHB591
Iref
8.2 k
All analog and digital supply ground pins are connected internally and should be connected via a massive external ground plate. (1) TP1, TP2, TEST1 and TEST2 should be connected to VSSD during normal operation. (2) Lx: ferrite bead, e.g. BLM 31A601S (Murata).
Fig.9 External components (SDIP42 version).
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
handbook, full pagewidth
external input 470 nF 470 nF MONOIN
+5 V 3.3
2.2 F
47 F
470 nF
470 nF
Lx (2) SYSCLK 34 33 SCK VDDD3 35 VSSD3 36
VSSA4
EXTIR
OUTM
EXTIL
Vref2
P2
2.2 F 10 nF
44 OUTL 1
43
42
41
40
39
38
2.2 F
P1 37
OUTR 10 nF
2
32
WS
I2S-bus
+5 V
10
VDDA1
3
31
SDO
470 nF V SSA1
4
30
SDA I2C-bus
VSSD1 470 nF +5 V Lx (2) VSSD2
5
29
SCL
VDDD1
6
TDA9874AH
VDDA3 28
10 470 nF
+5 V
7 n.c.
27
VSSA3 1 F
8
26
CRESET
TP2
(1)
SIF1 9 25 Vref1
47 pF
NICAM
100 nF
50
10
24
TP1
(1)
11 12 PCLK 13 ADDR1 14 XTALO 15 XTALI 16 TP3 17 TEST2 18 Iref 19 ADDR2 20 VSSA2 21 VDEC 22 TEST1
23
SIF2
47 pF
50
(1)
470 nF 8.2 k decoupling capacitor
24.576 MHz
(1)
(1)
MHB592
All analog and digital supply ground pins are connected internally and should be connected via a massive external ground plate. (1) TP1, TP2, TP3, TEST1 and TEST2 should be connected to VSSD during normal operation. (2) Lx: ferrite bead, e.g. BLM 31A601S (Murata).
Fig.10 External components (QFP44 version).
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
13 PACKAGE OUTLINES SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
TDA9874A
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
ISSUE DATE 90-02-13 95-02-04
1999 Dec 03
60
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
TDA9874A
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1999 Dec 03
61
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
14 SOLDERING 14.1 Introduction
TDA9874A
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 14.3.2 WAVE SOLDERING
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 14.2.1 Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 MANUAL SOLDERING
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 14.3 14.3.1 Surface mount packages REFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 62
1999 Dec 03
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
14.4 Suitability of IC packages for wave, reflow and dipping soldering methods
TDA9874A
SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount BGA, SQFP HLQFP, HSQFP, HSOP, HTSSOP, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. suitable(2) not suitable not suitable(3) suitable not not recommended(4)(5) recommended(6) REFLOW(1) - suitable suitable suitable suitable suitable - - - - - DIPPING suitable
1999 Dec 03
63
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9874A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Dec 03
64
Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
NOTES
TDA9874A
1999 Dec 03
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
NOTES
TDA9874A
1999 Dec 03
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Philips Semiconductors
Preliminary specification
Digital TV sound demodulator/decoder
NOTES
TDA9874A
1999 Dec 03
67
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/01/pp68
Date of release: 1999
Dec 03
Document order number:
9397 750 05821

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